Real-time hardware/software co-design using devs-based transparent M&S framework

Design and development of hard Real-Time (RT) embedded systems present several crucial requirements regarding criticality and timeliness of these systems. Formal methods have been presented as a promising alternative to deal with the design issues of these applications. However, these formal method do not scale well in complex systems. Modeling and Simulation (M&S) provides cost-effective approaches to verify and validate the design and implementation details of complex RT applications. Nevertheless, M&S approaches and artifacts are usually discarded in the later phases of the development. Discrete Event Systems Specification (DEVS) provides an appropriate M&S framework to provide formal specifications to the actual RT system, incrementally moving from software specifications to a full hardware embedded system. In this work, we propose a hardware-in-the-loop model-driven method, based on DEVS for RT/embedded application/systems engineering. Our approach is based on an incremental substitution of DEVS virtual software models with Unix-compliant device files through a formally defined process in the modeling phase. Consequently, any DEVS simulation engine can be used. This paper advances the state-of-the-art in hardware-software co-design methodologies.